1. Field of the Invention
The present invention generally relates to a multilayer wiring substrate and a method of manufacturing the multilayer wiring substrate, and more particularly to a multilayer wiring substrate and a method for manufacturing the multilayer wiring substrate having a semiconductor element mounted on a layer structure in which a capacitor is formed on multiple layered wiring patterns.
2. Description of the Related Art
In recent years and continuing, densification is performed on nearly every portion of a semiconductor device (semiconductor element). Accordingly, when disposing wiring patterns proximal to each other, it is important to prevent cross-talk between wires and fluctuation of electric potential in power lines, for example. Particularly, in a case of a multilayer wiring substrate mounted with a high frequency semiconductor element for enabling a high speed switching operation, cross-talk noise is liable to occur as the frequency of the semiconductor element increases. Furthermore, the rapid on and off switching of a switching element(s) of the semiconductor element causes switching noise to occur. This increases the possibility of fluctuation of electric potential in, for example, the power lines.
Conventionally, as a method for solving the problems, a separate capacity element (e.g. chip capacitor) is mounted on a multilayer wiring substrate, so as to provide a bypass condenser for decoupling unwanted coupling among the circuits of, for example, signal lines and power lines.
The conventional configuration, however, has the following problems.    (1) There is less design freedom of wiring patterns by mounting a separate chip capacitor or the like.    (2) If the distance between the chip capacitor and the electrode of the semiconductor element is long, inductance will increase. The increase of inductance prevents the chip capacitor from providing a sufficient decoupling performance. This causes a need to mount the chip capacitor or the like at a position as near as possible to the semiconductor element.    (3) The mounting position of the chip capacitor or the like is limited due to, for example, the size of the chip capacitor. Therefore, there is a limit in disposing the chip capacitor or the like at the vicinity of the semiconductor element.
Furthermore, mounting a capacity element (e.g. chip capacitor) on a multilayer wiring substrate causes difficulty in size-reduction/weight-reduction of the layer structure. This is contradictory to the current tendency toward further size-reduction and weight-reduction. Nevertheless, there is also a limit in size-reduction of the chip capacitor or the like.
In order to solve the foregoing problems, there is a method of obtaining a capacitor portion by electro-depositing a resin layer on a first wiring layer of an insulating substrate for using the resin layer as a dielectric layer, and thus using the first wiring layer and a second wiring layer including the resin layer formed on the insulating layer as electrode layers, respectively.
The multilayer wiring substrate fabricated by this method is able to provide a desired decoupling effect (controlling of crosstalk noise among wirings, potential change of power lines, etc.). Furthermore, since a portion that comprises the multilayer wiring substrate (first and second wiring layers, resin layer) also serves as the electrode layers and dielectric layer of the capacitor portion, size-reduction and cost-reduction of the multilayer wiring substrate can be achieved.
Furthermore, in fabricating the resin layer, a solvent, containing an organic resin dispersed in a colloidal state, is prepared in an electrolytic cell. Then, the insulating substrate having the first wiring layer formed thereto is steeped (dipped) into the electrolytic cell. Then, an electric field is applied between the first wiring layer and the electrolytic cell, thereby utilizing the electrophoresis of colloids caused by the applied electric field. In addition, the organic resin is mixed with an inorganic filler comprising a material of a high dielectric constant. This is shown in, for example, Japanese Laid-Open Patent Application No. 2003-68923.
However, the conventional multilayer wiring structure including the capacitor portion exhibits a capacitance change rate of −10% through 18% in the range of −55° C. through 125° C., as shown in FIG. 1. Furthermore, the resin layer serving as the dielectric layer has a temperature coefficient of 1555 ppm/° C. In this conventional multilayer wiring structure, an electro-deposition polyimide liquid containing high dielectric constant filler is used. The liquid contains a water-soluble polyimide resin being in a colloidal state along with minute particles of high dielectric constant inorganic filler uniformly dispersed therein. Further, a dielectric film including the liquid is deposited on a conductor and an electrode is formed on the dielectric film.
Therefore, the conventional multilayer wiring structure is unable to attain a stable capacitance change rate with respect to temperature in a case of forming the dielectric layer by employing a resin layer having high temperature coefficient. Furthermore, it is desired to maintain the capacitance change rate with respect to temperature at a constant value without having to rely on temperature change in high temperature ranges. Furthermore, improvement of temperature characteristics is desired, especially in a case where the multilayer wiring substrate including the capacitor portion is used for a filter circuit or the like.